IIT Delhi Develops India's First Indigenously Designed Micro-GPU

Researchers at the Electrical Engineering Department of IIT Delhi have built India's first working, indigenously designed micro-Graphics Processing Unit. The announcement was made on 24 September 2026. The chip design uses a custom floating-point GPU engine written entirely in Register Transfer Language and mapped onto a Spartan-7 Field Programmable Gate Array board. It is aimed at low-cost embedded uses such as industrial control displays, e-rickshaw dashboards and educational readers. The team plans an 8 to 16 core vector-style graphics processor and eventual fabrication on a 65 nanometre process. It is a notable step in reducing India's dependence on imported graphics chips.

What Happened

The Indian Institute of Technology Delhi announced on 24 September 2026 that its researchers had developed India's first working, indigenously designed micro-Graphics Processing Unit. The work came out of the Electrical Engineering Department. M.Tech students Nammi Akash and M. Ravi Teja carried out the design under the supervision of Professor Jayadeva and Professor Kaushik Saha. The students said their objective was to create a compact but genuinely programmable graphics-processing architecture suitable for FPGA implementation and future ASIC realisation.

When & Where

The announcement was made on 24 September 2026 at IIT Delhi, located in Hauz Khas in New Delhi. IIT Delhi is one of the Institutes of National Importance established under the Institutes of Technology Act, 1961. The work sits within India's wider push on semiconductor design capability, which is concentrated in design centres in Bengaluru, Hyderabad, Noida and the older IIT laboratories.

Who Is Involved

IIT Delhi Electrical Engineering Department — the laboratory where the micro-GPU was designed and demonstrated.
Nammi Akash and M. Ravi Teja — M.Tech students who led the design work.
Professor Jayadeva and Professor Kaushik Saha — the faculty members who supervised the project.
Ministry of Education — the ministry under which the Indian Institutes of Technology function.
Ministry of Electronics and Information Technology — the ministry that drives national semiconductor design programmes.

How It Works

The design begins with a hardware description written in Register Transfer Language, which specifies how data moves between registers and what logic operates on it at each clock cycle.
That description is compiled and mapped onto a Field Programmable Gate Array, in this case a Spartan-7 board, whose logic blocks can be rewired electronically to behave like the designed circuit.
Using an FPGA lets the team test a full working processor without paying for silicon fabrication, which is the single most expensive step in chip development.
The engine is built around floating-point arithmetic, which is what graphics rendering needs to handle the fractional coordinates and colour values that images are made of.
Being programmable rather than fixed-function means the same hardware can run different rendering programs, which is what separates a GPU from a simple display controller.
Once the architecture is stable on FPGA, the same design can be migrated to an application specific integrated circuit, where it becomes a permanent, faster and far more power-efficient chip.

Why It Matters

Strategic angle: graphics and accelerator chips are almost entirely imported, so an indigenous design capability reduces a critical dependence.
Scientific angle: a working programmable graphics pipeline built in an academic laboratory demonstrates end-to-end design capability, not just simulation.
Economic angle: the target applications are low-cost embedded devices, a segment where imported high-end GPUs are far too expensive to use.
Educational angle: the project was led by M.Tech students, which shows that advanced chip design skills are being built inside Indian institutes.

Historical Background

India has built processor design capability steadily rather than suddenly. Academic and public sector laboratories have produced indigenous processor families over the past decade, including work on open instruction set architectures. The national push gained pace with the approval of the India Semiconductor Mission in 2021, which combined incentives for fabrication, packaging and design. Design-linked incentive support was extended to start-ups and academic teams so that chip design would not depend on foreign electronic design automation access alone. The micro-GPU continues this line, but moves into graphics processing, an area where India had no indigenous design until now.

Previous Related Events

The India Semiconductor Mission was approved in 2021 to build fabrication, packaging and design capability in the country.
Indian academic and public laboratories have developed indigenous processor cores based on open instruction set architectures, which established the design methodology this project builds on.
Indigenous space-grade and embedded microprocessors developed in India in recent years demonstrated that fabrication-ready designs can emerge from domestic teams.

Static GK Connection

Graphics Processing Unit: a processor with many simple cores designed to perform the same operation on large blocks of data at once, which suits image rendering and, more recently, machine learning.
Field Programmable Gate Array: an integrated circuit whose internal logic connections can be configured after manufacture, used to prototype digital designs before committing to silicon.
Application Specific Integrated Circuit: a chip manufactured for one fixed purpose, faster and more power-efficient than an FPGA but expensive to design and impossible to modify.
Process node: the manufacturing generation of a chip, expressed in nanometres, where a nanometre is one billionth of a metre. A smaller node generally packs more transistors into the same area.
Floating-point arithmetic: a method of representing real numbers in a computer with a wide range of magnitudes, essential for graphics coordinates and scientific computation.

India & World Comparison

The global graphics processor market is dominated by a small number of firms based in the United States, and leading commercial GPUs are fabricated at process nodes far finer than 65 nanometres. The IIT Delhi design is therefore not a competitor to those products; it is a demonstration of indigenous design capability in a segment, embedded and low-cost graphics, where the commercial giants do not compete. Several countries, including China and members of the European Union, have similar publicly funded programmes to build domestic processor design capability. India's comparative strength lies in design talent rather than in fabrication capacity, which is why an FPGA-first, ASIC-later path is the practical route. No verified global ranking of indigenous GPU design capability exists.

Future Impact

The immediate next step is an 8 to 16 core vector-style graphics processor architecture.
An optimised compiler and graphics software toolchain will be developed alongside the hardware, since a processor without software support cannot be used.
Migration to a 65 nanometre application specific integrated circuit process node is the stated long-term target.
Success would open a path to affordable indigenous graphics silicon for embedded devices, industrial panels and educational hardware.

🔑 Key Points for Revision

IIT Delhi announced India's first working indigenously designed micro-GPU on 24 September 2026.
The work was done in the Electrical Engineering Department of IIT Delhi.
M.Tech students Nammi Akash and M. Ravi Teja led the design.
Professors Jayadeva and Kaushik Saha supervised the project.
The design uses a custom floating-point GPU engine written entirely in Register Transfer Language.
It was mapped onto a Spartan-7 Field Programmable Gate Array platform.
An FPGA is a reconfigurable integrated circuit used to prototype digital systems.
Applications include industrial control displays and low-cost human-machine interfaces.
Other uses are e-rickshaw dashboard navigators and inland-water navigation terminals.
Educational e-book readers are another identified application.
The next step is an 8 to 16 core vector-style graphics processor.
An optimised compiler and graphics software toolchain will accompany the hardware.
The long-term target is a 65 nanometre application specific integrated circuit process node.
The India Semiconductor Mission was approved in 2021.
IITs function under the Ministry of Education and were established under the Institutes of Technology Act, 1961.

🧠 Concept Link (Static GK Deep Dive)

Core Concept: From FPGA Prototype to ASIC Chip

Definition: an FPGA is a chip that can be reconfigured after manufacture, while an ASIC is a chip built permanently for one purpose.
Constitutional / Legal Basis: no constitutional provision governs chip design; the Institutes of Technology Act, 1961 governs the institute where this work was done.
Scientific / Economic Principle: the design principle is hardware abstraction, where a circuit is first described in a hardware description language and only later committed to physical silicon.
Link to this event: the IIT Delhi micro-GPU was written in Register Transfer Language, demonstrated on a Spartan-7 FPGA, and is targeted at a 65 nanometre ASIC node later.
Origin & History: programmable logic devices have been used to prototype digital circuits for decades, and this workflow is now standard in chip design worldwide.
Key milestone 1: India approved the India Semiconductor Mission in 2021 to build design, fabrication and packaging capability.
Key milestone 2: indigenous processor cores based on open instruction set architectures were developed by Indian academic and public laboratories in the preceding years.
Related Acts / Schemes / Treaties: the India Semiconductor Mission; design-linked incentive support for chip design; the Institutes of Technology Act, 1961.
Nodal Ministry / Body: the Ministry of Electronics and Information Technology leads semiconductor policy; the Ministry of Education oversees the IITs.
India-specific relevance: India has strong chip design talent but limited fabrication capacity, so FPGA-based development is the practical path for academic teams.
Global comparison: leading commercial GPUs are fabricated at far finer nodes than 65 nanometres, so this project competes on capability demonstration rather than performance.
Data point: the planned next-generation design targets 8 to 16 cores in a vector-style architecture.
Common exam angle: examiners ask for the full forms of GPU, FPGA and ASIC, and the difference between a reconfigurable and a fixed-function chip.
Easy memory hook: "FPGA can be rewired, ASIC is written in stone."

❓ Practice MCQs

Q1. Which institute developed India's first working indigenously designed micro-GPU, announced on 24 September 2026? [Easy]

A) IIT Madras

B) IIT Delhi

C) IIT Bombay

D) IIT Kanpur

Answer: B

Explanation: The design came out of the Electrical Engineering Department of IIT Delhi.

Q2. What does the abbreviation FPGA stand for? [Easy]

A) Fast Processing Graphics Array

B) Fixed Program Gate Assembly

C) Field Programmable Gate Array

D) Floating Point Graphics Accelerator

Answer: C

Explanation: A Field Programmable Gate Array is a chip whose logic connections can be configured after manufacture.

Q3. On which FPGA platform was the IIT Delhi micro-GPU design mapped? [Moderate]

A) Spartan-7

B) Artix-3

C) Cyclone-10

D) Stratix-5

Answer: A

Explanation: The custom floating-point GPU engine was mapped onto a Spartan-7 FPGA platform.

Q4. The IIT Delhi team plans to migrate the design to which process node? [Moderate]

A) 7 nanometre

B) 28 nanometre

C) 65 nanometre

D) 180 nanometre

Answer: C

Explanation: The stated long-term target is fabrication on a 65 nanometre application specific integrated circuit process node.

Q5. In which language was the custom GPU engine of the IIT Delhi micro-GPU written? [Moderate]

A) Register Transfer Language

B) Assembly language

C) Structured Query Language

D) Hypertext Markup Language

Answer: A

Explanation: The engine was implemented entirely in Register Transfer Language before being mapped to the FPGA.

Q6. Which statement correctly distinguishes an FPGA from an ASIC? [Tricky]

A) An FPGA is manufactured for one fixed purpose, while an ASIC can be reconfigured after manufacture

B) An FPGA can be reconfigured after manufacture, while an ASIC is built permanently for one purpose

C) Both are reconfigurable, but an ASIC uses optical rather than electronic switching

D) Neither can be reconfigured; the difference lies only in the process node used

Answer: B

Explanation: This is why prototypes are built on FPGAs first and committed to an ASIC only once the design is stable.

Q7. Why is floating-point arithmetic important for a graphics processing unit? [Tricky]

A) It allows the chip to store text more compactly

B) It allows representation of real numbers across a wide range of magnitudes, as needed for coordinates and colour values

C) It reduces the number of transistors required on the chip

D) It allows the chip to operate without an external power supply

Answer: B

Explanation: Rendering works on fractional coordinate and colour values, which require floating-point representation.

Q8. What is the planned configuration of the next-generation processor the IIT Delhi team intends to build? [Tricky]

A) A single-core scalar processor with a fixed-function pipeline

B) A 4 core processor with no software toolchain

C) An 8 to 16 core vector-style graphics processor with an optimised compiler and software toolchain

D) A 32 core general-purpose central processing unit

Answer: C

Explanation: The team plans an 8 to 16 core vector-style architecture together with its own compiler and graphics software toolchain.

📜 Previous Year Question Style (PYQ)

PYQ 1:

The term "process node", expressed in nanometres in semiconductor manufacturing, refers to:

A) The number of cores present on a processor

B) The manufacturing generation of a chip, where a smaller figure generally allows more transistors in the same area

C) The clock speed at which the processor operates

D) The number of instructions the processor can execute per cycle

Answer: B

Explanation: A nanometre is one billionth of a metre, and a smaller node generally packs more transistors into the same area.

PYQ 2:

Consider the following statements about the IIT Delhi micro-GPU:

It was designed in the Electrical Engineering Department of IIT Delhi.
The design was demonstrated on a Spartan-7 Field Programmable Gate Array platform.
The chip has already been fabricated on a 65 nanometre process node.

Which of the above statements is/are correct?

A) 1 only

B) 1 and 2 only

C) 2 and 3 only

D) All of the above

Answer: B

Explanation: Statements 1 and 2 are correct. Statement 3 is wrong because the 65 nanometre node is a stated future target, not a completed step.

PYQ 3:

Assertion (A): Academic teams designing processors often demonstrate their work on Field Programmable Gate Arrays rather than on fabricated chips.

Reason (R): Silicon fabrication is the most expensive step in chip development, while an FPGA allows a full working design to be tested without it.

A) Both A and R are true, and R is the correct explanation of A

B) Both A and R are true, but R is not the correct explanation of A

C) A is true but R is false

D) A is false but R is true

Answer: A

Explanation: The IIT Delhi micro-GPU follows exactly this route, running on a Spartan-7 board with an ASIC node as a later target.

✍️ Mains Answer Pointers

Question 1 (150 words): Explain the significance of academic chip design projects such as the IIT Delhi micro-GPU for India's semiconductor ambitions.

The micro-GPU announced on 24 September 2026 matters less for its raw performance than for what it proves. A team of M.Tech students, supervised by two faculty members, took a graphics processor from a Register Transfer Language description to a working demonstration on a Spartan-7 FPGA.

That is the full design cycle, and it is the part of the semiconductor value chain where India can compete immediately. Fabrication requires capital and years; design requires talent and tools, both of which Indian institutes already have.

The application choice reinforces the point. Industrial control displays, e-rickshaw dashboards and educational readers are segments where imported high-end graphics chips are simply too costly, so an indigenous low-cost design has a real market.

The gap is the software. A processor is unusable without a compiler and toolchain, which is why the team's plan to build these alongside the next 8 to 16 core design is the decisive part of the roadmap.

Question 2 (250 words): India has design talent but limited fabrication capacity. Examine this proposition with reference to recent indigenous chip development efforts.

India's semiconductor position has long been asymmetric. The country has a large pool of chip design engineers working for global firms, while almost all fabrication happens abroad. The India Semiconductor Mission, approved in 2021, was intended to address both ends by supporting fabrication, packaging and design together.

Recent academic work shows why the design end moves faster. The IIT Delhi micro-GPU, announced on 24 September 2026, was designed in the institute's Electrical Engineering Department by M.Tech students Nammi Akash and M. Ravi Teja under Professors Jayadeva and Kaushik Saha. It was written entirely in Register Transfer Language and demonstrated on a Spartan-7 Field Programmable Gate Array. No fabrication plant was needed at any stage.

This FPGA-first route is not a compromise. It is how chip design works everywhere: the architecture is proven on reconfigurable hardware, and only a stable design is committed to an application specific integrated circuit. The IIT Delhi team's 65 nanometre ASIC target follows that sequence.

The limits are equally clear. A 65 nanometre node is several generations behind the leading edge, and without domestic foundries even a finished design must be fabricated abroad. Software is the second constraint, since a graphics processor without a compiler and toolchain cannot be adopted by device makers.

The sensible way forward is to play to the existing strength while building the missing one. Sustained support for academic design teams, domestic access to design automation tools, and patient investment in fabrication and packaging would let design capability and manufacturing capacity converge over time.

⚠️ Examiner Trap

Trap 1: Students confuse an FPGA with an ASIC. The correct fact is that an FPGA can be reconfigured after manufacture, while an ASIC is built permanently for a single purpose.
Trap 2: A common wrong assumption is that the IIT Delhi micro-GPU has already been fabricated as a chip. The reality is that it was demonstrated on a Spartan-7 FPGA board, with a 65 nanometre ASIC node named as a future target.
Trap 3: Many students miss that a GPU is not merely a display controller. Always remember that a GPU is programmable, so the same hardware can run different rendering programs, which a fixed-function display controller cannot.

IIT Delhi Develops India's First Indigenously Designed Micro-GPU

What Happened

When & Where

Who Is Involved

IIT Delhi Electrical Engineering Department — the laboratory where the micro-GPU was designed and demonstrated.
Nammi Akash and M. Ravi Teja — M.Tech students who led the design work.
Professor Jayadeva and Professor Kaushik Saha — the faculty members who supervised the project.
Ministry of Education — the ministry under which the Indian Institutes of Technology function.
Ministry of Electronics and Information Technology — the ministry that drives national semiconductor design programmes.

How It Works

The design begins with a hardware description written in Register Transfer Language, which specifies how data moves between registers and what logic operates on it at each clock cycle.
That description is compiled and mapped onto a Field Programmable Gate Array, in this case a Spartan-7 board, whose logic blocks can be rewired electronically to behave like the designed circuit.
Using an FPGA lets the team test a full working processor without paying for silicon fabrication, which is the single most expensive step in chip development.
The engine is built around floating-point arithmetic, which is what graphics rendering needs to handle the fractional coordinates and colour values that images are made of.
Being programmable rather than fixed-function means the same hardware can run different rendering programs, which is what separates a GPU from a simple display controller.
Once the architecture is stable on FPGA, the same design can be migrated to an application specific integrated circuit, where it becomes a permanent, faster and far more power-efficient chip.

Why It Matters

Strategic angle: graphics and accelerator chips are almost entirely imported, so an indigenous design capability reduces a critical dependence.
Scientific angle: a working programmable graphics pipeline built in an academic laboratory demonstrates end-to-end design capability, not just simulation.
Economic angle: the target applications are low-cost embedded devices, a segment where imported high-end GPUs are far too expensive to use.
Educational angle: the project was led by M.Tech students, which shows that advanced chip design skills are being built inside Indian institutes.

Historical Background

Previous Related Events

The India Semiconductor Mission was approved in 2021 to build fabrication, packaging and design capability in the country.
Indian academic and public laboratories have developed indigenous processor cores based on open instruction set architectures, which established the design methodology this project builds on.
Indigenous space-grade and embedded microprocessors developed in India in recent years demonstrated that fabrication-ready designs can emerge from domestic teams.

Static GK Connection

Graphics Processing Unit: a processor with many simple cores designed to perform the same operation on large blocks of data at once, which suits image rendering and, more recently, machine learning.
Field Programmable Gate Array: an integrated circuit whose internal logic connections can be configured after manufacture, used to prototype digital designs before committing to silicon.
Application Specific Integrated Circuit: a chip manufactured for one fixed purpose, faster and more power-efficient than an FPGA but expensive to design and impossible to modify.
Process node: the manufacturing generation of a chip, expressed in nanometres, where a nanometre is one billionth of a metre. A smaller node generally packs more transistors into the same area.
Floating-point arithmetic: a method of representing real numbers in a computer with a wide range of magnitudes, essential for graphics coordinates and scientific computation.

India & World Comparison

Future Impact

The immediate next step is an 8 to 16 core vector-style graphics processor architecture.
An optimised compiler and graphics software toolchain will be developed alongside the hardware, since a processor without software support cannot be used.
Migration to a 65 nanometre application specific integrated circuit process node is the stated long-term target.
Success would open a path to affordable indigenous graphics silicon for embedded devices, industrial panels and educational hardware.

🔑 Key Points for Revision

IIT Delhi announced India's first working indigenously designed micro-GPU on 24 September 2026.
The work was done in the Electrical Engineering Department of IIT Delhi.
M.Tech students Nammi Akash and M. Ravi Teja led the design.
Professors Jayadeva and Kaushik Saha supervised the project.
The design uses a custom floating-point GPU engine written entirely in Register Transfer Language.
It was mapped onto a Spartan-7 Field Programmable Gate Array platform.
An FPGA is a reconfigurable integrated circuit used to prototype digital systems.
Applications include industrial control displays and low-cost human-machine interfaces.
Other uses are e-rickshaw dashboard navigators and inland-water navigation terminals.
Educational e-book readers are another identified application.
The next step is an 8 to 16 core vector-style graphics processor.
An optimised compiler and graphics software toolchain will accompany the hardware.
The long-term target is a 65 nanometre application specific integrated circuit process node.
The India Semiconductor Mission was approved in 2021.
IITs function under the Ministry of Education and were established under the Institutes of Technology Act, 1961.

🧠 Concept Link (Static GK Deep Dive)

Core Concept: From FPGA Prototype to ASIC Chip

Definition: an FPGA is a chip that can be reconfigured after manufacture, while an ASIC is a chip built permanently for one purpose.
Constitutional / Legal Basis: no constitutional provision governs chip design; the Institutes of Technology Act, 1961 governs the institute where this work was done.
Scientific / Economic Principle: the design principle is hardware abstraction, where a circuit is first described in a hardware description language and only later committed to physical silicon.
Link to this event: the IIT Delhi micro-GPU was written in Register Transfer Language, demonstrated on a Spartan-7 FPGA, and is targeted at a 65 nanometre ASIC node later.
Origin & History: programmable logic devices have been used to prototype digital circuits for decades, and this workflow is now standard in chip design worldwide.
Key milestone 1: India approved the India Semiconductor Mission in 2021 to build design, fabrication and packaging capability.
Key milestone 2: indigenous processor cores based on open instruction set architectures were developed by Indian academic and public laboratories in the preceding years.
Related Acts / Schemes / Treaties: the India Semiconductor Mission; design-linked incentive support for chip design; the Institutes of Technology Act, 1961.
Nodal Ministry / Body: the Ministry of Electronics and Information Technology leads semiconductor policy; the Ministry of Education oversees the IITs.
India-specific relevance: India has strong chip design talent but limited fabrication capacity, so FPGA-based development is the practical path for academic teams.
Global comparison: leading commercial GPUs are fabricated at far finer nodes than 65 nanometres, so this project competes on capability demonstration rather than performance.
Data point: the planned next-generation design targets 8 to 16 cores in a vector-style architecture.
Common exam angle: examiners ask for the full forms of GPU, FPGA and ASIC, and the difference between a reconfigurable and a fixed-function chip.
Easy memory hook: "FPGA can be rewired, ASIC is written in stone."

❓ Practice MCQs

Q1. Which institute developed India's first working indigenously designed micro-GPU, announced on 24 September 2026? [Easy]

A) IIT Madras

B) IIT Delhi

C) IIT Bombay

D) IIT Kanpur

Answer: B

Explanation: The design came out of the Electrical Engineering Department of IIT Delhi.

Q2. What does the abbreviation FPGA stand for? [Easy]

A) Fast Processing Graphics Array

B) Fixed Program Gate Assembly

C) Field Programmable Gate Array

D) Floating Point Graphics Accelerator

Answer: C

Explanation: A Field Programmable Gate Array is a chip whose logic connections can be configured after manufacture.

Q3. On which FPGA platform was the IIT Delhi micro-GPU design mapped? [Moderate]

A) Spartan-7

B) Artix-3

C) Cyclone-10

D) Stratix-5

Answer: A

Explanation: The custom floating-point GPU engine was mapped onto a Spartan-7 FPGA platform.

Q4. The IIT Delhi team plans to migrate the design to which process node? [Moderate]

A) 7 nanometre

B) 28 nanometre

C) 65 nanometre

D) 180 nanometre

Answer: C

Explanation: The stated long-term target is fabrication on a 65 nanometre application specific integrated circuit process node.

Q5. In which language was the custom GPU engine of the IIT Delhi micro-GPU written? [Moderate]

A) Register Transfer Language

B) Assembly language

C) Structured Query Language

D) Hypertext Markup Language

Answer: A

Explanation: The engine was implemented entirely in Register Transfer Language before being mapped to the FPGA.

Q6. Which statement correctly distinguishes an FPGA from an ASIC? [Tricky]

A) An FPGA is manufactured for one fixed purpose, while an ASIC can be reconfigured after manufacture

B) An FPGA can be reconfigured after manufacture, while an ASIC is built permanently for one purpose

C) Both are reconfigurable, but an ASIC uses optical rather than electronic switching

D) Neither can be reconfigured; the difference lies only in the process node used

Answer: B

Explanation: This is why prototypes are built on FPGAs first and committed to an ASIC only once the design is stable.

Q7. Why is floating-point arithmetic important for a graphics processing unit? [Tricky]

A) It allows the chip to store text more compactly

B) It allows representation of real numbers across a wide range of magnitudes, as needed for coordinates and colour values

C) It reduces the number of transistors required on the chip

D) It allows the chip to operate without an external power supply

Answer: B

Explanation: Rendering works on fractional coordinate and colour values, which require floating-point representation.

Q8. What is the planned configuration of the next-generation processor the IIT Delhi team intends to build? [Tricky]

A) A single-core scalar processor with a fixed-function pipeline

B) A 4 core processor with no software toolchain

C) An 8 to 16 core vector-style graphics processor with an optimised compiler and software toolchain

D) A 32 core general-purpose central processing unit

Answer: C

Explanation: The team plans an 8 to 16 core vector-style architecture together with its own compiler and graphics software toolchain.

📜 Previous Year Question Style (PYQ)

PYQ 1:

The term "process node", expressed in nanometres in semiconductor manufacturing, refers to:

A) The number of cores present on a processor

B) The manufacturing generation of a chip, where a smaller figure generally allows more transistors in the same area

C) The clock speed at which the processor operates

D) The number of instructions the processor can execute per cycle

Answer: B

Explanation: A nanometre is one billionth of a metre, and a smaller node generally packs more transistors into the same area.

PYQ 2:

Consider the following statements about the IIT Delhi micro-GPU:

It was designed in the Electrical Engineering Department of IIT Delhi.
The design was demonstrated on a Spartan-7 Field Programmable Gate Array platform.
The chip has already been fabricated on a 65 nanometre process node.

Which of the above statements is/are correct?

A) 1 only

B) 1 and 2 only

C) 2 and 3 only

D) All of the above

Answer: B

Explanation: Statements 1 and 2 are correct. Statement 3 is wrong because the 65 nanometre node is a stated future target, not a completed step.

PYQ 3:

Assertion (A): Academic teams designing processors often demonstrate their work on Field Programmable Gate Arrays rather than on fabricated chips.

Reason (R): Silicon fabrication is the most expensive step in chip development, while an FPGA allows a full working design to be tested without it.

A) Both A and R are true, and R is the correct explanation of A

B) Both A and R are true, but R is not the correct explanation of A

C) A is true but R is false

D) A is false but R is true

Answer: A

Explanation: The IIT Delhi micro-GPU follows exactly this route, running on a Spartan-7 board with an ASIC node as a later target.

✍️ Mains Answer Pointers

Question 1 (150 words): Explain the significance of academic chip design projects such as the IIT Delhi micro-GPU for India's semiconductor ambitions.

Question 2 (250 words): India has design talent but limited fabrication capacity. Examine this proposition with reference to recent indigenous chip development efforts.

⚠️ Examiner Trap

Trap 1: Students confuse an FPGA with an ASIC. The correct fact is that an FPGA can be reconfigured after manufacture, while an ASIC is built permanently for a single purpose.
Trap 2: A common wrong assumption is that the IIT Delhi micro-GPU has already been fabricated as a chip. The reality is that it was demonstrated on a Spartan-7 FPGA board, with a 65 nanometre ASIC node named as a future target.
Trap 3: Many students miss that a GPU is not merely a display controller. Always remember that a GPU is programmable, so the same hardware can run different rendering programs, which a fixed-function display controller cannot.